The present invention is directed to manufacturing objects. More particularly, the invention provides a method and resulting structure for integrating a chip structure onto a film of flexible material. Merely by way of example, the invention has been applied to integrated circuit chips provided on polymer based structures such as a film of parylene material. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other chip structures including discrete electronic components, micro-electrical mechanical systems (MEMS), nano-electrical mechanical systems (NEMS), displays, power supplies, biological chips, medical chips, and biomedical chips. Additionally, the integrated chip and film structures can be applied to the fields of electronics, life sciences, publishing, medicine, business, finance, and/or other areas of commerce and/or lifestyle.
Over the years, microelectronics have proliferated into many aspects of modern day life. In the early days, Robert N. Noyce invented the integrated circuit, which is described in “Semiconductor Device-and-Lead Structure” under U.S. Pat. No. 2,981,877. Integrated circuits evolved from a handful of electronic elements into millions and even billions of components fabricated on a small slice of silicon material. Such integrated circuits have been incorporated into and control many conventional devices, such as automobiles, computers, medical equipment, and even children's toys.
Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits. Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer.
An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials.
An example of such a process is packaging of such integrated circuit chip using molding and/or encapsulation techniques. More particularly, conventional integrated circuits are often diced into individual integrated circuit chips. Such chips are individually packaged mounted on lead frames using die attach and/or bonding techniques. The chip and lead frames are then encapsulated using injection molding processes. Such molding processes use epoxy based plastic materials that are often very durable, but hard and rigid. Lead frames must also often be bonded using wire bonding techniques to connect the individual integrated circuits to leads and/or connectors. Plastic encapsulating packages are often cumbersome, difficult to integrate with other devices, and are limited due to size and shape. Other limitations include lack of biocompatibility, hermeticity, and general degradation in salt/water environments, among others. These and other limitations will be described in further detail throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing materials is desired.